The present invention relates to a semiconductor device of multi-level wiring structure such as a logic LSI (Logical Large Scale Integrated Circuit), a DRAM (Dynamic Random Access Memory), SRAM (Static RAM), a CMOS (Complementary Metal Oxide Semiconductor) or a bipolar transistor (Bipolar Transistor), especially, to a formation of multi-level wiring which includes via-contact formation using wiring formation and a conductive pillar-shaped structure (pillar), and a semiconductor device which has a multi-level wiring structure.
Conventionally, in general, when a connection plug, which electrically connects between the wirings of the upper level and the lower level in the multi-level wiring structure of the semiconductor device, is formed, a method of opening a contact hole by using a reactive ion etching (RIE (Reactive Ion Etching)) method etc. for an interlevel insulation film, and forming the connection plug by burying a conductive material such as metal is used.
This conventional art has the following disadvantages. At the RIE for the opening of the contact hole, physical damage and corrosion are caused on the surface of lower level wiring exposed to the bottom of the contact hole with the etching gas and the sputtered particle. A contact resistance between the above-mentioned connection plug and the lower level wiring rises by adhering the etching residue and the sputtered particle. When the contact hole is not formed at a desired position by the occurrence of the missalignment with the lower wiring pattern at formation of the contact hole, the lower wiring side and the interlevel insulation film thereunder are excessively etched by RIE. In addition, the undesirable short-circuit with the wiring of the lower level is occurs, and the cave remains around a fine wiring. As a result, the reliability lowers.
When the lower level wiring is formed, a method of forming a conductive pillar-shaped structure (pillar) and the lower level wiring at the same time is known. This method is a method of depositing a metal film on the insulation film formed on the semiconductor substrate, forming the connection plug with a photolithography and the etching methods such as an RIE and leaving a metal film in the trench to form the lower level wiring. However, the lower level wiring is the same material as the connection plug, and changing both of the material cannot broaden the variety of the selection of the material. Moreover, when the connection plug is etched, the lower level wiring might be over-etched. In addition, the missalignment might be occurred when the connection plug and the upper level wiring are connected.
Recently a high speed operation has come to be requested to the device. Therefore, a lower resistance material is required as for the wiring material. Copper (Cu) has been paid attention so as to respond to the request and is multi-used. The electrical resistivity of the copper is 1.8 xcexcxcexa9cm, and it is greatly low among the wiring material. Besides this, tungsten (W) whose resistivity is 10 to 20 xcexcxcexa9cm and aluminum (Al) whose resistivity is 3 to 4 xcexcxcexa9cm are used well as a wiring material. Therefore, AlCu alloy is used as any of the lower level wiring 12, the connection plug 14 (conductor pillar), and the upper level wiring 18 shown in FIG. 1A and FIG. 1B, for example, but is considered that the wiring resistance is reduced by using Cu for the lower level wiring 12 and the upper level 18, and using Al for the connection plug 14.
However, the inconvenience might happen when Cu is used as it is. First, Cu has characteristics to diffuse into the insulation film in the state of the atom when Cu is covered by the insulation film. Especially, the moving of Cu becomes active if Cu is heated by the use of the device and the heat-treating step under manufacturing, then the wiring is destroyed and comes to cause the disconnection and the short-circuit accident easily. Moreover, the surface is oxidized when Cu is exposed in (the) air, and advantage of the low resistance is lost.
Moreover, in the above-mentioned pillar technology, since the pillar-shaped structure (pillar) is formed only to connection part of the lower level wiring and the upper level wiring, the ratio of the region where the pillar-shaped structure is formed becomes very small and is about several % or less of the whole. Therefore, the pillar-shaped structure is excessively etched, for example, when the drying etching, and the processing of the pillar-shaped structure becomes difficult. The planarity of the interlevel insulation film formed after processing of the pillar-shaped structure deteriorates.
As described above, since the ratio of the region where the pillar-shaped structure is formed is very small when the pillar technology is used for the connection of the lower level wiring and the upper level wiring, there is a subject matter of a bad processing control of the pillar-shaped structure and a bad planarity of the interlevel insulation film.
An object of the present invention is as follows.
(1) To provide a semiconductor device manufacturing method having the multi-level wiring structure which can secure the space, in which the contact structure between the lower level wiring and the upper level wiring is arranged, before depositing the interlevel insulation film, can prevent from the damage at RIE and impurities on the surface of wiring under the contact hole, and can secure the reliability with the contact of the lower level wiring even if the missalignment is occurred at the contact hole.
(2) To provide a semiconductor device manufacturing method which has the multi-level wiring structure to connect between wirings in which the protection film to control the diffusion of the wiring material into the insulation film (or, to control the oxidation of the wiring material) can be deposited without greatly increasing steps, and the semiconductor device manufactured by the method.
(3) To provide a manufacturing method capable of improving the processing controllability and the planarity of the interlevel insulation film of the pillar-shaped structure (pillar) when the pillar technology is used to connection step of the lower level wiring and the upper level wiring.
According to the first aspect of the present invention, in the semiconductor device manufacturing method or the semiconductor device, a hard mask is formed on upper portion of the pillar, the process is advanced with leaving the hard mask, and the hard mask is removed immediately before connecting the pillar with the upper level wiring, when the lower level wiring (the first buried wiring) and the upper level wiring (the second wiring) are connected with the pillar-shaped structure (pillar). Where, it is desirable to form a protection film on the surface of the lower level wiring uncovered with at least the pillar-shaped structure after the pillar-shaped structure is formed.
The hard mask may be a silicon oxide, a silicon nitride, or a tungsten.
The first aspect of the present invention comprises the following features. First, after the first buried wiring (lower level wiring) which consists of Cu is formed on the first interlevel insulation film, a conductive layer, in which the connection plug which consists of, for example, Al/W/WN or Cu, etc. is formed, is formed. Next, this conductive layer is processed to the connection plug by the lithography technology and the RIE method. That is, in the first aspect of the present invention, a hard mask materials such as the silicon nitride film or the silicon oxide film for forming the connection plug is deposited as an etching mask on a conductive layer where the connection plug is formed. The protection film such as silicon nitride films (Si3N4) with an effect by which the diffusion of Cu to the interlevel insulation film is controlled and an effect by which the oxidation of the Cu surface is controlled is deposited on the connection plug and the first interlevel insulation film by the CVD method or the reactive sputtering method, etc. as desired thickness if necessary. Thereafter, the second interlevel insulation film is deposited, the upper level wiring is buried in the second interlevel insulation film. As a result, the lower level wiring and the upper level wiring are connected by the connection plug.
In addition, since the protection film which has a Cu diffusion prevention effect and an oxidation control effect in the region where the connection plug on the first buried wiring (lower level wiring) does not exist is deposited, and neither the first buried wiring (lower level wiring) nor the interlevel insulation film are not contacted directly unlike the conventional ones, an excellent characteristic is obtained without requiring the complicated steps. Both of the hard mask and the protection film also have an advantage of enlarging the difference allowance in the depth direction when the second wiring trench is processed.
Therefore, the difference allowance in the depth direction is enlarged, and the poor coverage of the barrier metal of the upper level is prevented by the present invention. In addition, the Cu diffusion from the lower level wiring can be prevented according to the present invention.
The upper surface of the pillar to take the electric contact with the wiring can be prevented from oxidizing during the process, being polluted, and occurring the chemical reaction by leaving a hard mask until the formation of the second wiring trench.
In the second aspect of the present invention, a semiconductor device comprises: a semiconductor substrate in which a first insulation layer having a trench where a lower level wiring is buried is formed; a conductive layer having a component which includes a barrier metal function formed on the lower level wiring; a conductive pillar-shaped structure which is connected with the conductive layer and is formed on the semiconductor substrate; and a second insulation layer formed on the semiconductor substrate in order to surround the pillar-shaped structure, and the second insulation layer has a trench formed to expose an upper portion of the pillar-shaped structure. And, an upper level wiring which is electrically connected with the pillar-shaped structure is formed in the trench.
The preferred manner of the second aspect is as follows.
(1) The conductive layer has at least two layers. Or, the conductive layer includes WN, and, desirably, the conductive layer further includes W. The connection plug on the first buried wiring (lower level wiring) has, for example, Al which is a main material of the connection plug and a conductive layer to prevent from over-etching to the first buried wiring when the Al is processed to the pillar-shaped structure by the RIE processing. In addition, when each material of the first buried wiring and the connection plug is different, for example, Cu as the wiring material and Al as the plug material. For example, WN can be applied as a conductive layer to meet this requirement, but since the WN has a high resistivity, the WN raises the entire resistance of the connection plug when a necessary film thickness is formed to have enough stopper function. Therefore, preferably, W which has only the stopper function and the electrical resistivity thereof is small is stacked thereto. As a result, the connection plug having the stopper function and the barrier function as W and WN stacking film, and low resistance can be formed. That is, the above-mentioned advantage is achieved by which the conductive layer has at least first and second layers, the first layer of the conductive layer functions as an etching stopper and a barrier layer when the pillar-shaped structure is processed, and the second layer of the conductive layer has a lower resistance than the first layer of the conductive layer, and functions as an etching stopper when the pillar-shaped structure is processed.
(2) The surface of the lower level wiring and the first insulation layer is substantially in the same plane, the conductive layer is formed so as to be connected with at least a part of the lower level wiring, and the semiconductor device further comprises a protection film covering the surface of the lower level wiring which is uncovered with the pillar-shaped structure and formed to be deposited on an upper portion of the pillar-shaped structure. The allowance becomes large since the protection film can be used as a position alignment allowance between the second wiring trench bottom and the upper surface of the pillar in the depth direction.
(3) The conductive layer is formed in the trench to cover all surfaces of the lower level wiring. Though the lower level wiring is covered with the protection film for preventing the Cu diffusion in (2), there is an advantage of reducing the capacity between the wirings since it is unnecessary to cover the upper surface of the wiring with the protection film having high permittivity (for example, SiN).
(4) The conductive layer includes the material which can be selectively etched for the first insulation film. Where, a horizontal section of the pillar-shaped structure is narrower than a horizontal section of the conductive layer. The pillar-shaped structure or the conductive layer has the shape of widening toward the end. The protection film formed to cover a sidewall of the pillar-shaped structure, the lower level wiring, and the first insulation layer is further provided.
(5) The pillar-shaped structure includes copper or an alloy thereof.
(6) The conductive layer is used as a CMP stopper when the lower level wiring is formed by the CMP.
According to the second aspect of the present invention, the protection film which has a Cu diffusion prevention effect and an oxidation control effect is deposited in the region where the connection plug on the first buried wiring (lower level wiring) does not exist, and since neither the first buried wiring (lower level wiring) nor the interlevel insulation film are not contacted directly unlike the conventional ones, an excellent characteristic can be obtained without requiring the complicated steps. In addition, the protection film consisting of the silicon nitride film deposited on the connection plug, also has the same function as the hard mask which enlarges the difference allowance in the depth direction when the second wiring trench is processed.
Moreover, since the narrow space between connection plug and the side of the second wiring trench, which is formed when the position of the bottom of the upper level wiring is lower than an uppermost surface of the connection plug, is not made, a coverage degradation etc. of the barrier metal of the upper level wiring in this part are prevented.
A part of the bottom of the connection plug shifts from the lower level wiring because of miss alignment when the connection plug is formed on the lower level wiring with borderless structure (without fringe at the connection region for a alignment allowance). Then, over-hanging shape is optionally provided under the connection plug by forming a conductive layer, which has a broader horizontal section than the pillar-shaped structure, on the first interlevel insulation film to surely achieve the protection film formation on this part, and the protection film with high reliability which can surely cover and protect the connection plug is formed.
According to the present invention, in the multi-level wiring structure interconnected by using a pillar-shaped connection plug, the formation of the protection film to which the entire pillar is covered becomes possible. The possibility of the metal material which can be selected as the connection plug extends, and, for example, the material with an extremely low electrical resistivity like copper can be selected.
According to the third aspect of the present invention, a semiconductor device comprises a plurality of pillar-shaped structures formed in connection regions where a lower level wiring and an upper level wiring are electrically connected, a plurality of dummy pillar-shaped structures formed in predetermined regions except the connection regions, and an interlevel insulation film formed to cover the plurality of pillar-shaped structures, wherein layout data of the dummy pillar-shaped structures formed in the predetermined regions are obtained by a NOR processing of corresponding data to both information which are based on a layout information of layout of the lower level wiring and layout information of layout of the upper level wiring. Where, the pillar-shaped structures formed in the connection regions and the predetermined regions are formed with the conductor.
Moreover, another semiconductor device according to the third aspect of the present invention comprises a plurality of pillar-shaped structures formed in connection regions where a lower level wiring and an upper level wiring are electrically connected, a plurality of dummy pillar-shaped structures formed in predetermined regions except the connection regions, and an interlevel insulation film formed to cover the plurality of pillar-shaped structures, wherein data of layout of the pillar-shaped structures formed in the predetermined regions is obtained by a NOT processing of data corresponding to the information based on layout information at the layout of the connection region.
The preferred manners of the third aspect of the present invention are as follows.
(1) The pillar-shaped structures formed in the connection regions are removed, after the interlevel insulation film is formed.
(2) The dummy pillar-shaped structures formed in the connection region and the predetermined regions are formed with an insulator.
(3) The dummy pillar-shaped structures formed in the predetermined regions are formed in regions except the predetermined specific regions.
According to the third aspect of the invention, the pillar-shaped structures (pillars) are formed in regions other than the connection regions where the lower level wirings and the upper level wirings are electrically connected. Therefore, the ratio of the regions where the pillar-shaped structures are formed can be greatly increased locally and/or overall, the processing controllability of the pillar-shaped structures, which is difficult in conventional ones, can be improved, and the planarity of the interlevel insulation film can be improved.
The layout of the pillar-shaped structures (dummy pillar-shaped structures) formed in the predetermined regions except the connection regions can be determined by the following arithmetic processing.
The method of the first arithmetic processing is a method of performing a NOR processing of data corresponding to both information which are based on a layout information of layout of the lower level wiring and a layout information of layout of the upper level wiring. An OR processing of the data obtained by the above mentioned arithmetic processing with the data corresponding to the connection region is preformed, and a mask to form the pillar-shaped structures based on the data obtained by the OR processing is manufactured. The mask pattern data, which corresponds to the dummy pillar-shaped structures, can be generated by performing the processing divided the region corresponding to the data obtained for example by the NOR processing into the plurality of island-shaped regions which are mutually separated.
The pillar-shaped structure is formed in the regions where neither the lower level wiring nor the upper level wiring are arranged besides the connection region of the lower level wiring and the upper level wiring by the pattern transfer using the mask thus manufactured. Therefore, the ratio of the region where the pillar-shaped structures are formed can be increased locally and/or overall.
When the pillar-shaped structures are formed by using the mask manufactured by the first arithmetic processing method, it is also possible to leave the pillar-shaped structures without removing after the interlevel insulation film is formed since the pillar-shaped structures are not formed in the regions where the lower level wirings and the upper level wirings are arranged. Therefore, the pillar-shaped structures formed in the connection regions and the predetermined regions except connection regions are formed with the conductor, and the pillar-shaped structures formed in connection regions can be used as the connection material of the lower level wirings and the upper level wirings.
The second arithmetic processing method is performing NOT processing of data corresponding to the information which is based on the layout information of the layout of connection regions of the lower level wiring and the upper level wiring. The OR processing of data obtained by the above mentioned arithmetic processing and data corresponding to connection regions is performed, and the mask to form the pillar-shaped structures based on the data obtained by this OR processing is manufactured. For example, the mask pattern data corresponding to the dummy pillar-shaped structures can be generated by performing the processing which divides the region corresponding to data obtained by a NOT processing into the plurality of island-shaped regions being mutually separated.
The pillar-shaped structures can be formed in all regions except connection regions of the lower level wiring and the upper level wiring by transferring the pattern using the mask manufactured described above. That is, it is different from the first arithmetic processing method, and it becomes possible to form the pillar-shaped structures in the regions where the lower level wirings and the upper level wirings are arranged. Therefore, the ratio of the region where the pillar-shaped structures are formed can become larger than the first arithmetic processing method.
When the pillar-shaped structures are formed in the predetermined regions except connection regions by the manufacturing method, for example, the first arithmetic processing method or the second arithmetic processing method, the pillar-shaped structures in the predetermined regions may be formed only in the regions except the predetermined specific regions (specific circuit region).
That is, when the layout of the pillar-shaped structures are determined by the arithmetic processing, the dummy pattern of the pillar-shaped structures is not generated for the predetermined specific region. Specifically, the dummy pattern is prevented from being generated for an undesirable specific regions, in which the dummy pillar-shaped structures are formed, in the circuit performance and the chip characteristic.
For example, the following regions are given as specific regions where the dummy pattern is not generated. First, regions where the circuit influenced by the parasitic capacity caused by the interlevel insulation film is arranged can be given. Regions where the spare circuit section, the redundancy circuit section, and the fuse section arranged in the circuit section are formed can be also given. In addition, regions where the terminal section (PAD section) for an external connection is formed and other regions where the dicing line section is provided can be given as specific regions.
As described above, according to the present invention, the pillar-shaped structures are formed in regions other than connection regions where the lower level wiring and the upper level wiring are electrically connected. Therefore, the ratio of the region where the pillar-shaped structure is formed can be greatly increased locally and overall, a processing controllability by pillar-shaped structure which is difficult conventionally can be improved, and improving the planarity of the interlevel insulation film becomes possible.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.